A gate array device which allows a LSI designer to program and implement a desired circuit, or a FPGA (Field Programmable Gate Array), has become popular. The most prospective among the programmable elements for FPGA is an antifuse element. The programming voltage Vpp of an antifuse element needs to be set so that Vpp/2 is higher than the supply voltage for the logic circuit. Therefore, for programming an antifuse element, a so called high breakdown voltage transistor whose drain breakdown voltage is higher than the logic circuit supply voltage is required.
A conventional integrated circuit device is described in the following with reference to FIG. 3(a) through FIG. 3(d), using its manufacturing method as the vehicle.
Among various elements of FPGA, FIG. 3 illustrates the cross sectional structure of a standard N-channel type MOS transistor constituting a logic circuit (hereinafter referred to as an N-channel standard transistor or simply as a standard transistor) and an N-channel type high breakdown voltage MOS transistor for programming in an antifuse element (hereinafter referred to as an N-channel high breakdown voltage transistor or simply as a high breakdown voltage transistor).
FIG. 3(a) shows oxide film etching process for forming a gate insulation film of a specified thickness for each of the N-channel standard transistor and the N-channel high breakdown voltage transistor; on a P-type monocrystal silicon substrate 1 a P-well region 2, a thick silicon oxide film 3 for separating elements and a channel dope region 4 are provided. After a first gate insulation film 5 is formed, at least a region for forming an N-channel high breakdown voltage transistor is covered with a first resist film 6, and a gate insulation film (not shown) on a region for forming a N-channel standard transistor is selectively removed by a buffered hydrofluoric acid etc.
Then, as shown in FIG. 3(b), a second gate insulation film 7 is formed after the first resist film 6 is removed, and a polycrystalline silicon 8 doped with N-type impurities such as phosphorus is grown to make a gate electrode.
Then, as FIG. 3(c) shows, a first gate electrode 9 for high breakdown voltage transistor and a second gate electrode 10 for standard transistor are formed by selectively etching off the polycrystalline silicon film 8. And then, using the gate electrode 9 and the gate electrode 10 as the mask, an N.sup.- -type diffusion layer region 12 which is to become an offset diffusion layer and an N.sup.- -type diffusion layer region 13 which is to become an LDD are formed by a self-aligned ion-implantation of N-type impurities 11 such as phosphorus.
Then, as shown in FIG. 3(d), the first gate electrode 9 and the second gate electrode 10 are provided respectively with a first side wall spacer 14 and a second side wall spacer 15. By ion-implanting N-type impurities 17 such as arsenic using a second resist film 16 as the mask, an N.sup.- -type offset diffusion layer 18, an N+-type source region 19 and an N+-type drain region 20 are formed for the high breakdown voltage transistor; at the same time, an N.sup.- -type LDD diffusion layer 21, an N+-type source region 22 and an N+-type drain region 23 are formed for the standard transistor.
In the above described conventional semiconductor integrated circuit device, the standard transistor and the high breakdown voltage transistor share the channel dope region 4 in common; as a result, there is a problem that if the impurity concentration in the channel dope region is raised for suppressing the short channel effect of standard transistor the drain breakdown voltage of the high breakdown voltage transistor goes down.
There are still other problems that the dispersion in the dimensions of the second resist film 16, the displacement of mask and other factors bring about a dispersion in the dimensions of the N.sup.- -type offset diffusion layer 18, which results in a dispersion in the electrical characteristics of high breakdown voltage transistor, particularly in the drain breakdown voltage and the saturation current. On the other hand, if the layout of transistor cell is determined taking the dispersion in processing into consideration for improving the electrical characteristics, the cell area inevitably goes larger, creating a new problem.